Process development toward enhancement-mode strained-Si/SiGe double quantum dot

Si has emerged as a promising material platform for solid-state quantum computation. Si/SiGe epitaxial technologies have enabled atomically smooth interfaces which lead to boosted two- dimensional electron mobility over conventional Si metal-oxide-semiconductor field-effect transistors (FETs). Enhancement-mode Si/SiGe heterostructures, which do not contain intentional dopants, provide electrons an even cleaner and quieter environment, which is an essential element for successful quantum computation. In this talk, we present our recent efforts in process development toward enhancement-mode strained Si/SiGe double quantum dots, utilizing either a 150mm Si foundry at wafer-level or a modern cleanroom setting at die-level. We focus on the following aspects: choice of gate insulator, device stability, and thermal budget. In the Si foundry, several types of dielectric stacks were deposited on strained Si/SiGe wafers as the gate insulator. It was found that low-pressure chemical-vapor-deposition (LPCVD) Si3N4 serves the purpose, in spite of its hysteretic behavior. Device with other types of dielectric stacks did not behave as FETs. At die-level, atomic-layer- deposition (ALD) Al2O3 was also tested as the gate dielectric. Functioning FETs were fabricated and showed improved negligible drifting against gate sweeping. Figure 1 (a) and (b) show the transistor characteristics of a device with 50 nm LPCVD Si3N4 and a device with 50 nm ALD Al2O3, respectively. Mobility and stability of the devices were found to be dependent on the thickness of the SiGe barrier layer. Figure 2 shows the density dependence of mobility for two wafers with 35 nm and 153 nm SiGe barrier layers. While a thicker SiGe barrier layer leads to higher electron mobility, it is also correlated with a poorer device stability. From self-consistent Schrodinger-Poisson simulations, we believe that the instability originates from a non-equilibrium electron distribution at cryogenic temperatures. Effects of thermal treatments were evaluated by analyzing samples receiving different thermal budget with secondary-ion-mass-spectrometry (SIMS) and x-ray diffraction. Figure 3 shows the depth profile of Ge obtained by SIMS for 4 samples annealed at different temperatures. It was found that a 900C rapid thermal annealing for 3 min causes diffusion of Ge into the strained Si layer, while a 850C annealing does not affect the Ge profile significantly. The minimum temperature required to activate implanted dopants was studied by rapid thermal annealing samples at different temperatures. It was found that 700C for 10 sec was sufficient to produce reliable ohmic contacts at 4K. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE, Office of Basic Energy Sciences user facility. The work was supported by the Sandia National Laboratories Directed Research and Development Program. Sandia National Laboratories is a multi- program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000. © 2012 IEEE.