Abstract
Using a new technique in forming the cubic single-crystal silicon nanoparticles that are about 40 nm on a side, the authors have demonstrated a vertical-flow surround-gate Schottky-barrier transistor. This approach allows the use of well-known approaches to surface passivation and contact formation within the context of deposited single-crystal materials for device applications. It opens the door to the novel three-dimensional integrated circuits and new approaches to hyper integration. The fabrication process involves successive deposition and planarization and does not require nonoptical lithography. Device characteristics show reasonable turn-off characteristics and on-current densities of more than 10 7 A/ cm 2. © 2006 IEEE.
| Original language | English |
|---|---|
| Pages (from-to) | 2525-2531 |
| Number of pages | 7 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 53 |
| Issue number | 10 |
| DOIs | |
| State | Published - Dec 1 2006 |
| Externally published | Yes |
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